<html><body><samp><pre>
<!@TC:1498768271>
#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec  2 2016
#install: C:\lscc\iCEcube2.2017.01\synpbase
#OS: Windows 8 6.2
#Hostname: LAPOT

# Thu Jun 29 23:31:11 2017

#Implementation: rgb_led_Implmnt

<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498768272> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

<a name=compilerReport2></a>Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498768272> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\generic\sb_ice40.v" (library work)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v" (library work)
Verilog syntax check successful!
Selecting top level module top
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\iCEcube2.2017.01\synpbase\lib\generic\sb_ice40.v:4110:7:4110:21:@N:CG364:@XP_MSG">sb_ice40.v(4110)</a><!@TM:1498768272> | Synthesizing module SB_LED_DRV_CUR in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\iCEcube2.2017.01\synpbase\lib\generic\sb_ice40.v:4036:7:4036:17:@N:CG364:@XP_MSG">sb_ice40.v(4036)</a><!@TM:1498768272> | Synthesizing module SB_RGB_DRV in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:1:7:1:10:@N:CG364:@XP_MSG">top.v(1)</a><!@TM:1498768272> | Synthesizing module top in library work.

<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:2:18:2:24:@W:CG133:@XP_MSG">top.v(2)</a><!@TM:1498768272> | Object o_leds is declared but not assigned. Either assign a value or remove the declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:3:13:3:21:@W:CL246:@XP_MSG">top.v(3)</a><!@TM:1498768272> | Input port bits 7 to 3 of i_switch[7:0] are unused. Assign logic for all port bits or change the input port size.</font>
@A:<a href="@A:CL153:@XP_HELP">CL153</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:2:18:2:24:@A:CL153:@XP_MSG">top.v(2)</a><!@TM:1498768272> | *Unassigned bits of o_leds[7:0] are referenced and tied to 0 -- simulation mismatch possible.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:4:7:4:15:@N:CL159:@XP_MSG">top.v(4)</a><!@TM:1498768272> | Input i_p21but is unused.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Jun 29 23:31:11 2017

###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498768272> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498768272> | Selected library: work cell: top view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498768272> | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Jun 29 23:31:12 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Jun 29 23:31:12 2017

###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498768273> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498768273> | Selected library: work cell: top view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498768273> | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Jun 29 23:31:13 2017

###########################################################]
Pre-mapping Report

# Thu Jun 29 23:31:13 2017

<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec  5 2016 10:31:39</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1498768275> | No constraint file specified. 
@L: D:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\rgb_led_scck.rpt 
Printing clock  summary report in "D:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\rgb_led_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1498768275> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1498768275> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=18  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)



<a name=mapperReport6></a>Clock Summary</a>
*****************

Start      Requested     Requested     Clock      Clock               Clock
Clock      Frequency     Period        Type       Group               Load 
---------------------------------------------------------------------------
System     1.0 MHz       1000.000      system     system_clkgroup     0    
===========================================================================

Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1498768275> | Writing default property annotation file D:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\rgb_led.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 46MB peak: 133MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 29 23:31:15 2017

###########################################################]
Map & Optimize Report

# Thu Jun 29 23:31:15 2017

<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec  5 2016 10:31:39</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1498768308> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1498768308> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1498768308> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)



@S |Clock Optimization Summary


<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks



##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 133MB)

Writing Analyst data base D:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\synwork\rgb_led_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 129MB peak: 133MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1498768308> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1498768308> | Synopsys Constraint File capacitance units using default value of 1pF  
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1498768308> | Writing EDF file: D:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\rgb_led.edf 
L-2016.09L+ice40

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 130MB peak: 133MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)

<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\drive\projects\lattice fpga\projects\reg_led\top.v:13:11:13:21:@W:MT246:@XP_MSG">top.v(13)</a><!@TM:1498768308> | Blackbox SB_RGB_DRV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\drive\projects\lattice fpga\projects\reg_led\top.v:9:15:9:27:@W:MT246:@XP_MSG">top.v(9)</a><!@TM:1498768308> | Blackbox SB_LED_DRV_CUR is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Thu Jun 29 23:31:48 2017
#


Top view:               top
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1498768308> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1498768308> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary10></a>Performance Summary</a>
*******************


Worst slack in design: 1000.000

@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1498768308> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
                   Requested     Estimated     Requested     Estimated                  Clock      Clock          
Starting Clock     Frequency     Frequency     Period        Period        Slack        Type       Group          
------------------------------------------------------------------------------------------------------------------
System             1.0 MHz       NA            1000.000      0.000         1000.000     system     system_clkgroup
==================================================================================================================
@N:<a href="@N:MT582:@XP_HELP">MT582</a> : <!@TM:1498768308> | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 





<a name=clockRelationships11></a>Clock Relationships</a>
*******************

Clocks            |    rise  to  rise      |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack     |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------
System    System  |  1000.000    1000.000  |  No paths    -      |  No paths    -      |  No paths    -    
===========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo12></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport13></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************

                 Starting                                                    Arrival             
Instance         Reference     Type               Pin       Net              Time        Slack   
                 Clock                                                                           
-------------------------------------------------------------------------------------------------
LED_CUR_inst     System        SB_LED_DRV_CUR     LEDPU     led_power_up     0.000       1000.000
=================================================================================================


<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************

               Starting                                                Required             
Instance       Reference     Type           Pin       Net              Time         Slack   
               Clock                                                                        
--------------------------------------------------------------------------------------------
RGB_DRIVER     System        SB_RGB_DRV     RGBPU     led_power_up     1000.000     1000.000
============================================================================================



<a name=worstPaths16></a>Worst Path Information</a>
<a href="D:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\rgb_led.srr:srsfD:\Drive\Projects\Lattice FPGA\Projects\reg_led\rgb_led\rgb_led_Implmnt\rgb_led.srs:fp:18295:18565:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      0.000
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     1000.000

    Number of logic level(s):                0
    Starting point:                          LED_CUR_inst / LEDPU
    Ending point:                            RGB_DRIVER / RGBPU
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                        Pin       Pin               Arrival     No. of    
Name               Type               Name      Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
LED_CUR_inst       SB_LED_DRV_CUR     LEDPU     Out     0.000     0.000       -         
led_power_up       Net                -         -       0.000     -           1         
RGB_DRIVER         SB_RGB_DRV         RGBPU     In      -         0.000       -         
========================================================================================
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)


Finished timing report (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:02s; Memory used current: 131MB peak: 133MB)

---------------------------------------
<a name=resourceUsage17></a>Resource Usage Report for top </a>

Mapping to part: ice5lp2ksg48
Cell usage:
SB_LED_DRV_CUR  1 use
SB_RGB_DRV      1 use
SB_LUT4         0 uses

I/O ports: 21
I/O primitives: 12
SB_IO          12 uses

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)
Total load per clock:

@S |Mapping Summary:
Total  LUTs: 0 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:02s; Memory used current: 24MB peak: 133MB)

Process took 0h:00m:33s realtime, 0h:00m:02s cputime
# Thu Jun 29 23:31:48 2017

###########################################################]

</pre></samp></body></html>
